The present invention relates to a mounting technique for integrated circuit (IC) chips (referred to below simply as “chips”) and, more specifically, to determining the thickness of an interposer on which a chip is mounted.
In high heat density chip mounting, where a chip is laminated three-dimensionally and mounted using face-down bonding, a low-cost organic substrate is typically used (instead of an inorganic substrate such as a ceramic) as the supporting substrate on which the flip chip is mounted.
However, because of the significant difference in thermal expansion coefficients between a silicon flip chip and an organic substrate, the thermal stress due to the significant difference in thermal expansion coefficients may cause the solder-joined portion to be destroyed when an organic substrate is used.
A mounting structure 100 is shown in FIG. 1. In this mounting structure 100, a silicon interposer 110 may be provided on an organic supporting substrate 105, and a silicon laminated chip 115 and top chip 120 may be mounted on the interposer 110. The top chip 120 is connected electrically on the obverse surface of the interposer 110 via a through-hole 125 provided inside the laminated chip 115. The reverse surface of the interposer 110 is connected to the supporting substrate 105 via electrodes 135, and an underfill 140 is provided between the supporting substrate 105 and the interposer 110. The joined portion 130 of the interposer 110 and the laminated chip 115 is more susceptible to destruction than other joined portions because it is closest to the supporting substrate 105, and the frequency of thermal stress occurring is highest when a number of chips are laminated individually.
Therefore, when an organic substrate with a high thermal expansion coefficient is used as a supporting substrate, a means of reducing the stress on the joined portion of the interposer and the chip is desired in order to perform chip mounting more reliably. The uppermost chip has been adjusted in order to reduce the stress on the joined portion, but this technique relies on the experience of the chip's designer. Because it relies on the experience of the designer, it is difficult to automate so that it can be performed by somebody other than the designer.
The laminated structure is optimized by directly determining the stress on the joined portion of the interposer and the chip in a laminated structure including a supporting substrate, an interposer, and a chip. The stress on the joined portion can be determined, for example, by performing a parameter analysis using the finite element method (FEM). This technique requires a high degree of expertise, and the modelling and calculations take time. Also, one-off calculations are essentially performed on each model, and this technique is difficult to automate so that it can be applied to different models.